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Data Sheet No. PD60240 revA
IRS20124S(PbF) DIGITAL AUDIO DRIVER WITH DISCRETE DEAD-TIME AND PROTECTION
Features
* 200V high voltage ratings deliver up to 1000W
output power in Class D audio amplifier applications Integrated dead-time generation and bi-directional over current sensing simplify design Programmable compensated preset dead-time for improved THD performances over temperature High noise immunity Shutdown function protects devices from overload conditions Operates up to 1MHz 3.3V/5V logic compatible input
Product Summary
VSUPPLY IO+/200V max. 1A / 1.2A typ.
* * * * * *
Selectable Dead Time 15/25/35/45ns typ. Prop Delay Time Bi-directional Over Current Sensing 70ns typ.
Package
14-Lead SOIC
Typical Application Diagram
<20V <200V IN <20V OC
IN OCSET 1 DT/SD OCSET 2 OC COM NC NC VB HO VS NC VCC
SD
LO
IRS 20124
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IRS20124S(PbF)
Description
The IRS20124S is a high voltage, high speed power MOSFET driver with internal dead-time and shutdown functions specially designed for Class D audio amplifier applications. The internal dead time generation block provides accurate gate switch timing and enables tight dead-time settings for better THD performances. In order to maximize other audio performance characteristics, all switching times are designed for immunity from external disturbances such as VCC perturbation and incoming switching noise on the DT pin. Logic inputs are compatible with LSTTL output or standard CMOS down to 3.0V without speed degradation. The output drivers feature high current buffers capable of sourcing 1.0A and sinking 1.2A. Internal delays are optimized to achieve minimal dead-time variations. Proprietary HVIC and latch immune CMOS technologies guarantee operation down to Vs= -4V, providing outstanding capabilities of latch and surge immunities with rugged monolithic construction.
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. All currents are defined positive into any lead. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions.
Symbol
VB Vs VHO VCC VLO VIN VOC VOCSET1 VOCSET2 dVs/dt Pd RthJA TJ TS TL
Definition
High side floating supply voltage High side floating supply voltage High side floating output voltage Low side fixed supply voltage Low side output voltage Input voltage OC pin input voltage OCSET1 pin input voltage OCSET2 pin input voltage Allowable Vs voltage slew rate Maximum power dissipation Thermal resistance, Junction to ambient Junction Temperature Storage Temperature Lead temperature (Soldering, 10 seconds)
Min.
-0.3 VB-20 Vs-0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -55 -
Max.
220 VB+0.3 VB+0.3 20 Vcc+0.3 Vcc+0.3 Vcc+0.3 Vcc+0.3 Vcc+0.3 50 1.25 100 150 150 300
Units
V V V V V V V V V V/ns W C/W
C C C
2
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IRS20124S(PbF)
Recommended Operating Conditions
For Proper operation, the device should be used within the recommended conditions. The Vs and COM offset ratings are tested with all supplies biased at 15V differential.
Symbol
VB VS VHO VCC VLO VIN VOC VOCSET1 VOCSET2 TA
Definition
High side floating supply absolute voltage High side floating supply offset voltage High side floating output voltage Low side fixed supply voltage Low side output voltage Logic input voltage OC pin input voltage OCSET1 pin input voltage OCSET2 pin input voltage Ambient Temperature
Min.
Vs+10 Note 1 Vs 10 0 0 0 0 0 -40
Max.
Vs+18 200 VB 18 VCC VCC VCC VCC VCC 125
Units
V V V V V V V V V C
Note 1: Logic operational for VS equal to -8V to 200V. Logic state held for VS equal to -8V to -VBS.
Dynamic Electrical Characteristics
VBIAS (VCC, VBS) = 15V, CL = 1nF and TA = 25C unless otherwise specified. Figure 2 shows the timing definitions.
Symbol
ton toff tr tf tsd toc twoc min toc filt DT1 DT2 DT3 DT4
Definition
High & low side turn-on propagation delay High & low side turn-off propagation delay Turn-on rise time Turn-off fall time Shutdown propagation delay Propagation delay time from Vs>Vsoc+ to OC OC pulse width OC input filter time Deadtime: LO turn-off to HO turn-on (DTLO-HO) & HO turn-off to LO turn-on (DTHO-LO) Deadtime: LO turn-off to HO turn-on (DTLO-HO) & HO turn-off to LO turn-on (DTHO-LO) Deadtime: LO turn-off to HO turn-on (DTLO-HO) & HO turn-off to LO turn-on (DTHO-LO) Deadtime: LO turn-off to HO turn-on (DTLO-HO) & HO turn-off to LO turn-on (DTHO-LO)VDT= VDT4
Min. Typ.
-- -- -- -- -- -- -- -- 0 5 10 15 60 60 25 15 140 280 100 200 15 25 35 45
Max. Units Test Conditions
80 80 40 35 200 -- -- -- 40 50 60 70
nsec
VS=0V VS=200V
OCSET1=3.22V OCSET2=1.20V
VDT>VDT1 VDT1>VDT> VDT2 VDT2>VDT> VDT3 VDT3>VDT> VDT4 3
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IRS20124S(PbF)
Static Electrical Characteristics
VBIAS (VCC , VBS) = 15V and TA = 25C unless otherwise specified.
Symbol
VIH VIL VOH VOL UVCC+ UVCCUVBS+ UVBSIQBS IQCC ILK IIN+ IINIo+ IoVDT1 VDT2 VDT3 VDT4 VSOC+ VSOC-
Definition
Logic high input voltage Logic low input voltage High level output voltage, VBIAS - VO Low level output voltage, VO Vcc supply UVLO positive threshold Vcc supply UVLO negative threshold High side well UVLO positive threshold High side well UVLO negative threshold High side quiescent current Low side quiescent current High to Low side leakage current Logic "1" input bias current Logic "0" input bias current
Min.
2.5 -- -- -- 8.3 7.5 8.3 7.5 -- -- -- -- --
Typ.
-- -- -- -- 9.0 8.2 9.0 8.2 -- -- -- 3 0
Max. Units Test Conditions
-- 1.2 1.2 0.1 9.7 8.9 9.7 8.9 1 4 50 10 1.0 Vcc=10~20V Io=0A Io=0A
V
mA
A
VDT =Vcc VB=VS =200V VIN =3.3V VIN =0V Vo=0V, PW<10S Vo=15V, PW<10S
Output high short circuit current (Source) -- 1.0 -- Output low short circuit current (Sink) -- 1.2 -- DT mode select threshold 1 0.8xVcc 0.89xVcc 0.97xVcc DT mode select threshold 2 0.51xVcc 0.57xVcc 0.63xVcc DT mode select threshold 3 DT mode select threshold 4 Positive OC threshold in Vs Negative OC threshold in Vs 0.32xVcc 0.36xVcc 0.40xVcc 0.21xVcc 0.23xVcc 0.25xVcc 0.75 1.0 1.25 -1.25 -1.0 -0.75
A
V
OCSET1=3.22V OCSET2=1.20 OCSET1=3.22V OCSET2=1.20V
4
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IRS20124S(PbF)
Lead Definitions
Symbol Description
VCC VB HO VS IN DT/SD COM LO OC OC SET1 OC SET2 Low side logic Supply voltage High side floating supply High side output High side floating supply return Logic input for high and low side gate driver outputs (HO and LO), in phase with HO Input for programmable dead-time, referenced to COM. Shutdown LO and HO when tied to COM Low side supply return Low side output Over current output (negative logic) Input for setting negative over current threshold Input for setting positive over current threshold
1 2 3 4 5 6 7
IN
NC 14
OCSET1 NC 13 DT/SD OCSET2 OC COM LO VB 12 HO 11 VS 10 NC VCC 9 8
IR20124S 14 Lead SOIC (narrow body)
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IRS20124S(PbF)
Block Diagram
VB
UV DETECT LEVEL SHIFTER DEAD TIME S R UV Q
HO
IN
SD
VS
CURRENT SENSING
DT/SD
UV DETECT
Vcc
LO
DELAY
COM
6
OCSET2
OCSET1
OC
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IRS20124S(PbF)
IN
50% ton(L) toff(H) 90%
50%
toff(L) ton(H)
HO 10% DTHO-LO LO DTLO-HO 90%
10%
Figure 1. Switching Time Waveform Definitions
DT/SD
VSD
HO LO
90%
TSD
Figure 2. Shutdown Waveform Definitions
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IRS20124S(PbF)
LO
COM
toc filt
VS
VSoc+ COM VSoc-
VS
Vsoct COM HIGH
OC
tdoc
OC
COM
Figure 3. OC Input FilterTime Definitions
twoc
Figure 4. OC Waveform Definitions
IN
NC
OCSET1 NC DT/SD VB 15V Vsoc+ Vsoc15V
10k
OCSET2 HO __ OC VS COM LO NC VCC
OC
Vsoc+
VS
COM Vsoc-
OC
Figure 5. OC Waveform Definitions
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200 Turn-on Delay Time (ns) 160 120 80 40 0 -50 -25 0 25 50
o
200 Turn-on Delay Time (ns) 75 100 125 160 120 80 40 0 10 12 14 16 18 20 Temperature ( C) Figure 6A. Turn-On Tim e vs. Tem perature V BIAS Supply Voltage (V) Figure 6B. Turn-On Tim e vs. Supply Voltage
150 Turn-Off Time (ns) Turn-Off Time (ns) 120 90 60 Typ. 30 0 -50 Max.
150 120 90 60 30 0 -25 0 25 50 75 100 125 10 12 14 16 18 20 Temperature (oC) Figure 7A. Turn-Off Time vs. Temperature V BIAS Supply Voltage (V) Figure 7B. Turn-Off Time vs. Supply Voltage Typ. Max.
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IRS20124S(PbF)
60 Turn-On Rise Time (ns) Turn-On Rise Time (ns) -25 0 25 50 75 100 125 50 40 30 20 10 -50
60 50 40 30 20 10 10 12 14 16 18 20 Temperature ( oC) Fiure 8A. Turn-On Rise Tim e vs.Tem perature V BIAS Supply Voltage (V) Figure 8B. Turn-On Rise Tim e vs. Supply Voltage
50 Turn-Off Fall Time (ns) 40 30 20 10 0 -50 -25 0 25 50
o
50 Turn-Off Fall Time (ns) 75 100 125 40 30 20 10 0 10 12 14 16 18 20 Temperature ( C) Figure 9A. Turn-Off Fall Tim e vs. Tem perature V BIAS Supply Voltage (V) Figure 9B. Turn-Off Fall Tim e vs. Supply Voltage
10
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IRS20124S(PbF)
5 Input Voltage (V)
5 Input Voltage (V) 4 3 2 1
-50 -25 0 25 50 75 100 125
4 3 2 1 Temperature (oC) Figure 10A. Logic "1" Input Voltage vs. Tem perature Min.
Min.
10
12
14
16
18
20
V CC Supply Voltage (V) Figure 10B. Logic "1" Input Voltage vs. Supply Voltage
4 3 2 Max. 1 0 -50
4
Input Voltage (V)
Input Voltage (V) 0 25 50
o
3
2 Max. 1
-25
75
100
125
0 10 12 14 16 18 20
Temperatre ( C) Figure 11A. Logic "0" Input Voltage vs. Temperature
V CC Supply Voltage (V) Figure 11B. Logic "0" Input Voltage vs. Supply Voltage
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IRS20124S(PbF)
High Level Output Voltage (V)
3 2 1 0 -1 -50 Max.
High Level Output Voltage (V)
4
4 3 2 Max. 1 0 10 12 14 16 18 20 V CC Supply Voltage (V) Figure 12B. High Level Output vs. Supply Voltage
-25
0
25
50
75
100
125
Temperature (oC) Figure 12A. High Level Output vs. Temperature
Low Level Output Voltage (V)
0.25 0.20 0.15 Max. 0.10 0.05 0.00 -50 Low Level Output Voltage (V)
0.25 0.20 0.15 Max. 0.10 0.05 0.00 10 12 14 16 18 20 VCC Supply Voltage (V) Figure 13B. Low Level Output vs. Supply Voltage
-25
0
25
50
o
75
100
125
Temperature ( C) Figure 13A. Low Level Output vs.Temperature
12
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IRS20124S(PbF)
Offset Supply Leakage Current (A)
250 200 150 100 50 Max.
Offset Supply Leakage Current (A)
300
110 90 70 50 30 10 -10 50 80 110 140 170 200 V B Boost Voltage (V) Figure 14B. Offset Supply Leakage Current vs. Supply Voltage Typ. Max.
0 -50
-25
0
25
50
75
100
125
Temperature ( oC) Figure 14A. Offset Supply Leakage Current vs. Temperature V B=200v
2.5 ) ) V BS Supply Current ( 2.0 1.5 1.0 0.5 0.0 -50 -25 0 25 50 75 100 125 Temperature (oC) Figure 15A. V BS Supply Current vs. Tem perature V BS Supply Current (
3 2 2 1 1 0 10 12 14 16 18 20 V BS Supply Voltage (V) Figure 15B. V BS Supply Current vs. Supply Voltage
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IRS20124S(PbF)
10 V cc Supply Current (A) V cc Supply Current () 8 6 4 2 0 -50 Max.
10 8 6 4 2 0 -25 0 25 50 75 100 125 10 12 14 16 18 20 V CC Supply Voltage (V) Figure 16B. V CC Supply Current vs. Supply Voltage Max.
Temperature (oC) Figure 16A. V CC Supply Current vs. Temperature
)
30 Logic "1" Input Current ( -25 0 25 50 75 100 125 24 18 12 6 0 -50 )
30 24 18 12 6 0 10 12 14 16 18 20 V CC Supply Voltage (V) Figure 17B. Logic "1" Input Current vs. Supply Voltage
Logic "1" Input Current (
Temperature (oC) Figure 17A. Logic "1" Input Current vs. Tem perature
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IRS20124S(PbF)
Logic "0" Input Current ()
5 4 3 2 Max. 1 0 -50 Logic "0" Input Current () 0 25 50 75 100 125
5 4 3 2 Max. 1 0 10 12 14 16 18 20 V CC Supply Voltage (V) Figure 18B. Logic "0" Input Current vs. Supply Voltage
-25
Temperature (oC) Figure 18A. Logic "0" Input Current vs. Temperature
11 V cc Supply Current () 10 9 8 7 6 -50 Typ. Min. Max.
11 V cc Supply Current () 10 9 8 7 6 -50 Max. Typ. Min.
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
Temperature (oC) Figure 19. V CC Undervoltage Threshold (+) vs. Temperature
Temperature ( oC) Figure 20. V CC Undervoltage Threshold (-) vs. Temperature
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IRS20124S(PbF)
11 ) ) V BS Supply Current ( V BS Supply Current ( 10 9 8 7 6 -50 -25 0 25 50 75 100 125 Temperature (oC) Figure 21. V BS Undervoltage Threshold (+) vs. Tem perature
11 10 9 8 7 6 -50 -25 0 25 50
o
75
100
125
Temperature ( C) Figure 22. V BS Undervoltage Threshold (-) vs. Tem perature
1.5 Output Source Current () Output Sink Current ( ) 1.3 1.1 0.9 0.7 0.5 10 12 14 16 18 20 V BIAS Supply Voltage (V) Figure 23. Output Source Current vs. Supply Voltage Typ.
1.5 1.3 1.1 0.9 0.7 0.5 10 12 14 16 18 20 VBIAS Supply Voltage (V) Figure 24. Output Sink Current vs. Supply Voltage Typ.
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IRS20124S(PbF)
VS Offset Supply Voltage (V)
-5 -7 -9 -11 -13 -15 10 12 14 16 18 20 V BS Floting Supply Voltage (V) Figure 25. Maximum VS Negative Offset vs. Supply Voltage Typ. VDT 1(V)
16 15 14 13 12 Min. Max.
Typ.
11 -50
-25
0
25
50
o
75
100
125
Temperature ( C) Figure 26. DT mode select Threshold (1) vs. Temperature
11 10 VDT 2(V) 9 8 7 Typ. Min. Max. VDT 3(V)
8 7 6 5 4 Min. Max. Typ.
6 -50
-25
0
25
50
o
75
100
125
3 -50
-25
0
25
50
o
75
100
125
Temperature ( C) Figure 27. DT mode select Threshold (2) vs. Temperature
Temperature ( C) Figure 28. DT mode select Threshold (3) vs. Temperature
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IRS20124S(PbF)
4.5 4.0 DTLO-HO (nsec) VDT 4(V) 3.5 3.0 2.5 2.0 -50
60 52 44 36 28 20 -50 Typ.
-25
0
25
50
o
75
100
125
-25
0
25
50
o
75
100
125
Temperature ( C) Figure 29. DT m ode select Threshold (4) vs. Tem perature
Temperature ( C) Figure 30. DT LO turn-off to HO turn-on (3) vs. Tem perature
2.0 Positive OC TH(V) Negative OC TH(V) 1.6 Max. 1.2 0.8 0.4 0.0 -50 -25 0 25 50 75 100 125 Temperature ( oC) Figure 31. Positive OC Threshold(+) in VS vs. Tem perature Typ. Min.
-0.3 -0.6 -0.9 Typ. -1.2 -1.5 -1.8 -50 Min. Max.
-25
0
25
50
o
75
100
125
Temperature ( C) Figure 32. Negative OC Threshold(-) in VS vs. Temperature
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IRS20124S(PbF)
65
o Temperature ( C)
65 55 45 35 25 15 1 10 100 1000 1 10 100 1000 Frequency (KHZ) Frequency (KHZ) Figure 3 4 . IRS20124s vs. Frequency (IRFBC30) 33. Rgate=22 , V CC=12V
1 40v 70v 0v
o Temperature ( C)
55 45 35 25 15
1 40V 70V 0V
Figure 32. IRS20124s vs. Frequency (IRFBC20) 33. Rgate=33 , VCC=12V
65
o Temperature ( C)
75 65
o Temperature ( C)
1 40V 70V 0V
55 45 35 25 15 1 10 100
1 40V 70V 0V
55 45 35 25 15
1000
1
10
100
1000
Frequency (KHZ) Figure 3 5. IRS20124s vs. Frequency (IRFBC40) 34. Rgate=15 , V CC=12V
Frequency (KHZ) Figure 3 6. IRS20124s vs. Frequency (IRFPE50) 35. Rgate=10 , V CC=12V
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IRS20124S(PbF)
Functional description
Programmable Dead-time The IRS20124 has an internal dead-time generation block to reduce the number of external components in the output stage of a Class D audio amplifier. Selectable dead-time through the DT/SD pin voltage is an easy and reliable function, which requires only two external resistors. The dead-time generation block is also designed to provide a constant dead-time interval, independent of Vcc fluctuations. Since the timings are critical to the audio performance of a Class D audio amplifier, the unique internal dead-time generation block is designed to be immune to noise on the DT/SD pin and the Vcc pin. Noise-free programmable dead-time function is available by selecting deadtime from four preset values, which are optimized and compensated. How to Determine Optimal Dead-time Please note that the effective dead-time in an actual application differs from the dead-time specified in this datasheet due to finite fall time, tf. The deadtime value in this datasheet is defined as the time period from the starting point of turn-off on one side of the switching stage to the starting point of turn-on on the other side as shown in Fig.5. The fall time of MOSFET gate voltage must be subtracted from the dead-time value in the datasheet to determine the effective dead time of a Class D audio amplifier. (Effective dead-time) = (Dead-time in datasheet) - (fall time, tf)
90% HO (or LO)
Effective dead-time
10%
tf Deadtime 10%
Figure 6. Effective Dead-time
LO (or HO)
A longer dead time period is required for a MOSFET with a larger gate charge value because of the longer tf. A shorter effective dead-time setting is always beneficial to achieve better linearity in the Class D switching stage. However, the likelihood of shoot-through current increases with narrower dead-time settings in mass production. Negative values of effective dead-time may cause excessive heat dissipation in the MOSFETs, potentially leading to their serious damage. To calculate the optimal dead-time in a given application, the fall time tf for both output voltages, HO and LO, in the actual circuit needs to be measured. In addition, the effective dead-time can also vary with temperature and device parameter variations. Therefore, a minimum effective dead-time of 10nS is recommended to avoid shoot-through current over the range of operating temperatures and supply voltages.
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IRS20124S(PbF)
DT/SD pin DT/SD pin provides two functions: 1) setting deadtime and 2) shutdown. The IRS20124 determines its operation mode based on the voltage applied to the DT/SD pin. An internal comparator translates which mode is being used by comparing internal reference voltages. Threshold voltages for each mode are set internally by a resistive voltage divider off Vcc, negating the need of using a precise absolute voltage to set the mode. The relationship between the operation mode and the voltage at DT/SD pin is illustrated in the Fig.7.
Operational Mode
Deadtime mode DT1 DT2 DT3 DT4
R1 <10k 3.3k 5.6k 8.2k
R2 Open 8.2k 4.7k 3.3k
DT/SD voltage 1.0 x Vcc 0.71 x Vcc 0.46 x Vcc 0.29 x Vcc
Table 1. Suggested resistor values for dead-time settings
Shutdown Since IRS20124 has internal dead-time generation, independent inputs for HO and LO are no longer provided. Shutdown mode is the only way to turn off both MOSFETs simultaneously to protect them from over current conditions. If the DT/ SD pin detects an input voltage below the threshold, VDT4, the IRS20124 will output 0V at both HO and LO outputs, forcing the switching output node to go into a high impedance state. Over Current Sensing In order to protect the power MOSFET, IRS20124 has a feature to detect over current conditions, which can occur when speaker wires are shorted together. The over current shutdown feature can be configured by combining the current sensing function with the shutdown mode via the DT/SD pin. Load Current Direction in Class D Audio
15nS 25nS Dead-time 35nS 45nS Shutdown
0.23xVcc 0.36xVcc 0.57xVcc 0.89xVcc Vcc
VDT
Figure 7. Dead-time Settings vs VDT Voltage
Design Example Table 1 shows suggested values of resistance for setting the deadIRS20124 time. Resistors with >0.5mA Vcc up to 5% tolerance can be used if these R1 listed values are folDT/SD lowed.
R2 COM
Application
In a Class D audio amplifier, the direction of the load current alternates according to the audio input signal. An over current condition can therefore happen during either a positive current cycle or a negative current cycle. Fig.9 shows the rela21
Figure 8. External Resistor
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IRS20124S(PbF)
tionship between output current direction and the current in the low side MOSFET. It should be noted that each MOSFET carries a part of the load current in an audio cycle. Bi-directional current sensing offers over current detection capabilities in both cases by monitoring only the low side MOSFET.
Load Current
IRS20124 measures the current during the period when the low side MOSFET is turned on. Fig.10 illustrates how an excessive voltage at Vs node detects an over current condition. Under normal operating conditions, Vs voltage for the low side switch is well within the trip threshold boundaries, VSOC- and VSOC+. In the case of Fig.9(b) which demonstrates the amplifier sourcing too much current to the load, the Vs node is found below the trip level, VSOC-. In Fig.9(c) with opposite current direction, the amplifier sinks too much current from the load, positioning Vs well above trip level, VSOC+. Once the voltage in Vs exceeds the preset threshold, the OC pin pulls down to COM to detect an over current condition. Since the switching waveform usually contains over/under shoot and associated oscillatory artifacts on their transient edges, a 200ns blanking interval is inserted in the Vs voltage sensing block at the instant the low side switch is engaged. Because of this blanking interval, the OC function will be unable to detect over current conditions if the low side ON duration less than 200ns.
LO Vs
OCSET1 + -
0
Figure 9. Direction in MMOSFET Current and Load Current
Bi-directional Current Sensing IRS20124 has an over current detection function utilizing RDS(ON) of the low side switch as a current sensing shunt resistor. Due to the proprietary HVIC process, the IRS20124 is able to sense negative as well as positive current flow, enabling bi-directional load current sensing without the need for any additional external passive components.
vs
~ ~ Vsoc+ ~ ~ ~ ~ ~ ~ ~~ ~~ ~~ ~~ ~ ~ ~ ~ ~ ~
OR
OCSET2 + -
AND
OC
Figure 11. Simplified Functional Block Diagram of Bi-Directional Current Sensing
COM Vsoc-
(a ) Normal Operation Condition
(b ) Over- Current in Positive Load Current
(c ) Over- Current in Negative Load Current
Figure 10. Vs Waveform in Over-current Condition
As shown in Fig.11, bi-directional current sensing block has an internal 2.0V level shifter feeding the signal to the comparator. OCSET1 sets the positive side threshold, and is given a trip level at VSOC+, which is OCSET1 - 2.0V. In same way, for a given OCSET2, VSOC- is set at OCSET2 - 2.0V
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IRS20124S(PbF)
>0.5mA
Vcc R3 OCSET1 R4 OCSET2 R5 COM
threshold level is being set. Please also note that, in the negative load current direction, the sensing voltage at the Vs node is limited by the body diode of the low side MOSFET as explained later. Design Example This example demonstrates how to use the external? resistor network to set ITRIP+ and ITRIP- to be 11A, using a MOSFET that has RDS(ON) =60mU. VISET1 = VTH+ + 2.21 = ITRIP+ x RDS(ON) + 2.21= 11 x 60mU +2.21 = 2.87V VISET2 = VTH- + 2.21 = ITRIP- x RDS(ON) + 2.21= (-11) x 60mU +2.21 = 1.55V The total resistance of resistor network is based on the voltage at the Vcc and required bias current in this resistor network. Rtotal =R3 + R4 + R5 = Vcc / Ibias = 12V / 1mA = 12KU The expected voltage across R3 is Vcc- VISET1 = 12-2.87=9.13V. Similarly, the voltages across R4 is VSOC+ - VSOC- = 2.87-1.55=1.32V, and the voltage across R5 is VISET2= 1.55V respectively. R3 =9.13V/ Ibias = 9.13KU R4 =1.32V/ Ibias = 1.32KU R5 =1.55V/ Ibias = 1.55KU Choose R3= 9.09KU, R4=1.33KU, R5=1.54KU from E-96 series. Consequently, actual threshold levels are VSOC+ =2.88V gives ITRIP+ = 11.2A VSOC- =1.55V gives ITRIP- = -11.0A Resisters with 1% tolerances are recommended.
23
Figure 12. External Resistor Network to set OC Threshold
How to set OC Threshold The positive and negative trip thresholds for bidirectional current sensing are set by the voltages at OCSET1 and OCSET2. Fig.14 shows a typical resistor voltage divider that can. be used to set OCSET1 and OCSET2. The trip threshold voltages, VSOC+ and VSOC+, are determined by the required trip current levels, ITRIP+ and ITRIP-, and RDS(ON) in the low side MOSFET. Since the sensed voltage of Vs is shifted up by 2.21V internally and compared with the voltages fed to the OCSET1 and OCSET2 pins, the required value of OCSET1 with respect to COM is VOCSET1 = VSOC+ + 2.21 = ITRIP+ x RDS(ON) + 2.21 The same relation holds between OCSET2 and VSOC-, VOCSET2 = VSOC- + 2.21 = ITRIP- x RDS(ON) + 2.21 In general, RDS(ON) has a positive temperature coefficient that needs to be considered when the
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IRS20124S(PbF)
OC Output Signal The OC pin is a 20V open drain output. The OC pin is pulled down to ground when an over current condition is detected. A single external pull-up resistor can be shared by multiple IRS20124 OC pins to form the ORing logic. In order for a microprocessor to read the OC signal, this information is buffered with a mono stable multi vibrator to ensure 100ns minimum pulse width. Because of unpredictable logic status of the OC pin, the OC signal should be ignored during power up/down. Limitation from Body Diode in MOSFET When a Class D stage outputs a positive current, flowing from the Class D amp to the load, the body diode of the MOSFET will turn on when the Drain to Source voltage of the MOSFET become larger than the diode forward drop voltage. In such a case, the sensing voltage at the Vs pin of the IRS20124 is clamped by the body diode. This means that the effective Rds(on) is now much lower than expected from Rds(on) of the MOSFET, and the Vs node my not able to reach the threshold to turn the OC output on before the MOSFET fails. Therefore, the region where body diode clamping takes a place should be avoided when setting VSOC-.
Voltage in Vs
0
}
Load Current
Body Diode Clamp
Vsoc- should be set in this region
Figure 13. Body Diode in MOSFET Clamps vs Voltage
For further application information for gate driver IC please refer to AN-978 and DT98-2a. For further application information for class D application, please refer to AN-1070 and AN-1071.
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 322 3331 Data and specifications subject to change without notice. 9/21/2005
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